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Sr. Substrate CAD Layout Eng, Annapurna Labs, Machine Learning Hardware

Annapurna Labs (U.S.) Inc.
Cupertino, CA, 95014, USA
  • Engineering
  • Internship
  • PCB layout
  • substrate design
  • Cadence Allegro

Our job summary

Senior engineer responsible for substrate and PCB/layout design for next-generation ML ASICs, handling placement, routing, constraint management, and drafting for high-volume manufacturing. Collaborates with electrical engineers, fabrication and assembly vendors, and PLM to deliver manufacturable high-density PCBs and substrates using Cadence Allegro, SIP, and APD tools. Requires deep experience in high-speed/impedance circuits, HDI and BGA designs, assembly/test/fabrication knowledge, and process-driven design practices.


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